The manufacture of large scale integrated circuits in a mass production facility involves hundreds of discrete processing steps beginning with the introduction of blank semiconductor wafers at one end and recovering the completed chips at the other end. The manufacturing process is usually conceived as consisting of the segment wherein the semiconductor devices are formed within the silicon surface (front-end-of-line) and the portion which includes the formation of the various layers of interconnection metallurgy above the silicon surface (back-end-of-line). Most of these processing steps involve depositing layers of material, patterning them by photolithographic techniques and etching away the unwanted portions. These materials consist primarily of insulators and metal alloys.
In order to monitor the integrated circuit manufacturing process, test structures that are representative of the circuit elements are typically incorporated into regions of the wafer outside of the integrated circuit chips as product failures are closely correlated to test structure/site failures.
Examples of these in-line test devices are: a dumb-bell structure testable with a four point probe to establish proper resistivity of a deposited layer; or long serpentine metal lines which can be tested to establish the presence of particulate defects by testing for electrical opens and shorts. These devices are typically designed with critical areas much larger than their corresponding elements in the integrated circuit so they are more sensitive to defects and can be tested at various stages during processing. In addition to such devices which characterize the cleanliness and integrity of the process line, test sites must also be provided which can characterize the integrity of pattern alignment and planar dimensions.
Of particular interest is this invention is the ability to detect the formation of voids in buried (copper) interconnect lines. These voids are typically created by mechanical stresses which cause delamination of the metal line from the adjacent insulative matrix. The resulting void, while not directly producing an open circuit in the metal line, is nevertheless responsible for creating a hot spot when a current is passed through the line. Such hot spots encourage electromigration in the copper which in turn causes migration of the void along the line, eventually combining with other voids to form a larger void at a point where the metal lines meet a contact or via. The result is an “open” failure. It would therefore be desirable to have a means of early detection of hidden stress induced voids in metal lines.
Traditional test structures use the copper (Cu) volume effect (where more volume causes more micro-vacancies produced after baking) to dominate the SIV failure only.
U.S. Pat. No. 6,037,795 to Filippi et al. describes a multiple device test layout.
U.S. Pat. No. 6,191,481 to Bothra et al. describes electromigration impeding composite metallization lines and methods for making the same.
U.S. Pat. No. 5,973,402 to Shinriki et al. describes a metal interconnection and a method for making the same.
U.S. Pat. No. 5,504,017 to Yue et al. describes void detection in metallization patterns.
U.S. Pat. No. 5,156,909 to Henager, Jr. et al. describes thick, low-stress films, and coated substrates formed therefrom, and methods for making same.
U.S. Pat. No. 5,010,024 to Allen et al. describes passivation for integrated circuit structures.
U.S. Pat. Nos. 6,174,743 B1 and 6,221,794 B1, both to Pangrie et al., describe a method of reducing incidence of stress-induced voiding in semiconductor interconnect lines.